1. Field of the Invention
The present invention relates to a capacitance element for a semiconductor device and a method of manufacturing the same.
2. Description of the Prior Art
As a megabit VLSI dynamic memory or the like is implemented with a larger scale of integration, each of capacitance elements employed therein must be reduced in occupied area. However, such a capacitance element being simply reduced in occupied area cannot withstand external noise (particularly soft error caused by alpha rays), and hence it is impossible to unrestrictedly reduce the occupied area of the capacitance element.
Methods generally adopted to increase a capacitance value comprise a method of increasing an effective surface area where a capacitance is to be formed, and a method of inserting a material having a high dielectric constant between two surfaces forming a capacitance. The former method is considerably effective but involves an incompatible problem not easily solved by a simple increase of the effective area because reduction of an area occupied by a capacitance is required in a dynamic memory as described above. In the later method, Ta.sub.2 O.sub.5 for example is used as a material having a high dielectric constant but such a material as Ta.sub.2 O.sub.5 is liable to cause dielectric breakdown. Consequently, the latter method is not suited either.
Therefore, the so-called trench type capacitance element, provided in a trench formed in a substrate to be reduced in occupied area on the substrate, has been generally employed as a capacitance element for a memory device such as a dynamic RAM.
FIGS. 1 and 2 are a plan view and a sectional view, respectively, showing a structure of a memory cell of a conventional MIS (metal insulator semiconductor) dynamic RAM disclosed in Japanese Patent Laying-Open Gazette No. 239053/1985.
This memory cell comprises: a silicon substrate 101; a p.sup.+ diffusion layer 102; an oxide film 103; a groove 104 for forming a capacitor; an oxide film 105 outermost from the groove 104; a first polysilicon layer 106 inside the oxide film 105 to form the capacitor; a nitride film 107 formed inside the first polysilicon layer 106 for insulation of two poles of the capacitor; a contact 108; a second polysilicon layer 109 for forming the capacitor; a gate oxide film 110; a gate 111; n.sup.+ diffusion layers 112 and 113; an insulating film 114; a contact 115; a bit line 116; and a protection film 117. This memory cell of the dynamic RAM uses a trench type capacitance element.
FIG. 3 is a sectional view showing a trench type capacitance element of another conventional memory cell. The memory cell shown in FIG. 3 comprises a semiconductor substrate 1, an insulating film 2 such as an oxide film, a polysilicon layer 3, a conductive layer 4, a silicide layer 5 formed by barrier metal and an aluminum interconnection layer 6.
Conventional trench forms are roughly classified into two types. The first type is shown by a mask pattern in FIG. 4A in which the hatched portion is formed as a trench. The second type is shown by a mask pattern in FIG. 5A in which the hatched portion is formed as a trench. In order to more clearly indicate the forms of the trenches of those two types, a form of a conductive layer 4 in a lower portion of each trench will be described in the following.
FIG. 4B is a plan view of the conductive layer 4 of the trench formed by using the mask pattern shown in FIG. 4a; FIG. 4C is a sectional view taken along the line 4C--4C in FIG. 4B; and FIG. 4D is a perspective view of this conductive layer 4.
FIG. 5B is a plan view of the conductive layer 4 of the trench formed by using the mask pattern shown in FIG. 5A; FIG. 5C is a sectional view taken along the line 5C--5C in FIG. 5D; and FIG. 5D is a perspective view of this conductive layer.
Thus, the two types of trenches are conventionally used and in either case, a single trench is formed.
Although such a trench type capacitance element has a small opening area, an advantage is brought about that the capacitance component obtained by the same is substantially indentical to that of a non-trench type capacitance element.
However, the trench must be extremely deeply provided in the conventional trench type capacitance element. The depth of such a trench needs to be further increased if an opening area of an element is reduced without decreasing a capacitance value thereof in view of improvement in a scale of integration of a memory device. In order to cope with this, it is necessary to provide a dielectric film of high withstand voltage along the side wall of the trench, whereas it is extremely difficult in technique to form such a film. Thus, it has been substantially impossible to unrestrictedly reduce the opening area of the trench type capacitance element by increasing the depth of the trench in view of improvement in a scale of integration.
Under the circumstances, the U.S. Pat. No. 3,962,716 issued on June 8, 1976 to D. L. Kendail et al. entitled "Large Value Capacitor" purposes a solution of the above described problems, in which an effective surface area is increased by providing an increased number of trenches, i.e. more than one. However, according to this proposal, the trenches are formed by simply applying a conventional photolithographic etching process and consequently a spacing of the adjacent trenches or a width of each trench is limited to a value permissible for etching by the photolithographic process. As a result, a trench narrower than a width of a mask for etching cannot be formed, which imposes restrictions on improvement of a scale of integration and increase of a capacitance value.